Embodiments according to the invention are related to a re-configurable nest circuit for use in an automated test equipment and to a method for operating an automated test equipment. Further embodiments according to the invention are related to an apparatus, a method and a computer program for setting up an automated test equipment.
Some embodiments according to the invention are related, to an automated test equipment (ATE) with programmable protocol behavior.
Testing of devices is an increasingly important aspect in the fabrication of complex devices like, for example, systems on a chip. With increasing complexity of the devices under test, a creation of appropriate test programs for testing such devices is getting more and more difficult. Also, further difficulties arise from the fact that more and more devices comprise the ability to establish, on their own initiative, a communication with other devices or external components, in accordance with a communication protocol. In some cases, it is extremely difficult to predict when a device will make an attempt to establish communication in accordance with a communication protocol. In addition, in some cases it may be extremely difficult to predict details regarding a timing of a communication which is established based on the initiative of a device.
Some of the above described developments impose increasing difficulties on the testing of such devices.
In the following, some details regarding conventional testers (or test systems), which may in the following be designated as automated test equipment (ATE), will be described. Traditional automated nest equipment output predetermined test vectors (i.e. a set of states across pins) and compare an input (for example a sequence of input values) to predetermined vectors.
In the following, a conventional automated test equipment will be described taking reference to FIG. 10. FIG. 10 shows a block schematic diagram of a conventional automated test equipment. The automated test equipment shown in FIG. 10 is designated in its entirety with 1000. The automated test equipment 1000 comprises a test processor (TP) 1010 and a pin electronics circuit (PE) 1030. Moreover, the automated test equipment 1000 comprises a memory 1040. The test processor 1010 may be configured to provide one or more output signals 1012 to the pin electronics circuit 1030. In some cases, the test processor may also be configured to provide an output clock signal 1014 to the pin electronics circuit 1030. The pin electronics circuit 1030 may, for example, comprise an output buffer or output driver 1032, which may be configured to receive the output signal 1012 and, optionally, the central signal or output clock signal 1014, from the test processor 1010. The output driver or output buffer 1032 may for example be configured to provide an output signal to a device-under-test (DUT) connection 1034 of the pin electronics circuit 1030. For example, the output buffer or output driver 1032 may be configured to receive the output signal 1012 of the test processor 1010, which output signal 1012 may, for example, be a digital signal, and to provide a device-under-test signal at the device-under-test connection 1034 on the basis of the output signal 1012, wherein the output buffer or output driver 1032 may translate the levels of the output signal 1012 to levels necessitated by the device-under-test. For example, the output buffer or output driver 1032 may be configured to receive the output signal 1012 having predetermined logic levels, and to provide a device-under-test output signal having adjustable (logic) levels. In addition, the DUT driver or the DUT buffer 1032 may be configured no amplify the output signal 1012 and/or to provide a predetermined output impedance.
The output buffer or output driver 1032 may further be configured to store or latch the output signal 1012 in the response to the optional control signal or clock signal 1014.
Additionally, the output buffer or output driver 1032 may be configured to be switched into a high-impedance state or “tristate”-state in response to the control signal 1014. For example, when signals are to be received from a device-under-test via the device-under-test connection 1034, it may be desirable to deactivate the output buffer or output driver 1032, for example by putting the output buffer or output driver 1032 into high-impedance state or “tristate”-state.
The test processor 1010 may further be configured to receive an input signal 1016 from the pin electronics circuit 1030. For example, the pin electronics circuit 1030 may comprise the input buffer or input threshold circuit 1036 in order to provide the received signal or input signal 1016 in dependence on a device-under-test signal, which may be present at the device-under-test connection 1034. For example, the receive buffer or threshold circuit 1036 may be configured to compare the device-under-test input signal, which may be provided by the device-under-test to the device-under-test connection 1034, with one or more threshold levels. Accordingly, the receive signal 1016 provided by the receive buffer or threshold circuit 1036 may indicate whether the device-under-test input signal is above or below one or more of the threshold levels.
In the following, some details regarding the test processor 1010 will be described. The test processor 1010 may, for example, comprise a data sequencer 1050. The data sequencer 1050 may, for example, be coupled to the memory 1040 to receive from the memory 1040 a description 1052 of a bit stream to be generated. The data sequencer 1050 may further be configured to provide a device-under-test stimulus bit stream 1054 on the basis of the information 1052. For example, the data sequencer 1050 may be configured to decompress a compressed description of the bit stream, which may be represented by the information 1052, to obtain the device-under-test stimulus bit stream 1054. In addition, the data sequencer 1050 may comprise additional functionality like, for example, a loop processing functionality or a repetition-language processing-functionality. The test processor 1010 may further comprise a drive formatter 1060, which drive formatter 1060 may, for example, be configured to generate the output signal 1012 in dependence on (or in response to) the device-under-test stimulus bit stream 1054. For example, the drive formatter 1060 may be configured to provide, as the output signal 1012, a wave form having an adjustable timing. For example, each bit of the device-under-test stimulus bit stream 1054 may be mapped to a waveform section having one or more edges with adjustable timing. Further, the drive formatter 1060 may, for example, be configured to provide the control signal 1014 in dependence on the device-under-test stimulus bit stream 1054 or in dependence on an additional side-information.
Moreover, the data sequencer 1050 may, for example, be configured to provide an expected device-under-test response bit stream 1056, which may, for example, describe a bit stream, which is expected as a response of the device-under-test to a signal pattern forwarded to the device-under-test.
The test processor 1000 may also comprise a receive formatter 1070, which receive formatter may be configured to sample the receive signal 1016 provided by the pin electronics circuit 1030, at adjustable instances in time. The receive formatter 1070 may, for example, be configured to provide a device-under-test response bit stream 1072 based on the input signal 1016. In other words, the receive formatter 1070 may convert the input signal 1016 into a sampled digital bit stream 1072, taking into account, for example, a timing or a physical level encoding of the received input signal 1016.
The test processor 1000 may further comprise an error processing 1080, which may be configured to receive the expected response bit stream 1056 from the data sequencer 1050 and the actual device-under-test (response) bit stream 1072 from the receive formatter 1070. The error processing 1080 may further be configured to compare the expected device-under-test response bit stream 1056 with the actual device-under-test response bit stream 1072, to determine whether the actual device-under-test response bit stream 1072 is in agreement with the expected device-under-test response bit stream 1056. If the actual device-under-test response bit stream deviates from the expected device-under-test bit stream 1056 (which may optionally comprise “don't cares”), the error processor 1080 may, for example, provide an error signal 1082.
The test processor 1000 may further comprise a timing generator 1090. The timing generator 1090 may, for example, comprise a clock generator 1092, which may be configured to generate a clock signal or to provide a clock signal on the basis of an externally provided clock signal. For example, the clock generator 1092 may receive a clock signal and derive a derived clock signal from the received clock signal. For example, the clock generator 1092 may comprise a phase locked loop or a delay locked loop in order to derive a clock signal 1092a. The timing generator 1090 may further comprise one or more delay lines 1094. The one or more delay lines 1094 may, for example, be configured to derive timing signals from the clock signal 1092a to adjust the timing of the drive formatter 1060 and of the receive formatter 1070. For example, a timing of edges of the output signal 1012 (or of the signal provided to the device-under-test at the device-under-test connection 1034) may be adjustable by varying a delay of one of the delay lines 1094. In addition, a time when the receive signal or input signal 1016 is sampled in the receive formatter 1070 is adjustable by varying a delay of one of the delay lines 1094. Accordingly, both a timing of the signal output to the device-under-test via the device-under-test connection 1034 and a timing of an evaluation of a signal received from a device-under-test via the device-under-test connection 1034 is adjustable using the timing generator 1090.
The test processor 1000 may further, optionally, comprise a time-interval-analyzer 1098. The time-interval-analyzer 1098 may, for example, be configured to determine a frequency of an input signal or a time between edges of the input signal 1016.
Furthermore, the test processor may comprise different communication means to communicate with an environment. For example, the test processor 1000 may comprise an interface to obtain data from the memory 1040 for a use in the data sequencer 1050. Moreover, the test processor 1000 may be configured to provide error data (or pass/fail data) to the memory 1040. The error data or pass/fail data may, for example, be obtained by the error processor 1080. In addition, the test processor may be coupled to one or more control lines to provide to the one or more control lines, for example, an error information 1082. For example, the one or more control lines may act as a wired-AND or as a wired-OR to couple the test processor 1000 with one or more additional test processors not shown in FIG. 10. For example, the test processor may provide the error information or the pass/fail, information 1082 to one or more of the control lines, for example to synchronize an operation of two or more test processors. Moreover, the data sequencer 1050 may be coupled to the one or more control lines, to be controlled by the one or more control lines.
Moreover, the test processor 1000 may comprise an interface 1099 for communication with a work station, or with any other means for providing control information to the test processor 1000.
To summarize the above, an example of a test processor for use in an automated test equipment has been described taking reference to FIG. 10.
Further aspects regarding test systems are described in some additional documents.
For example, US 2007/0266288 A1 describes an automated test system including one or more re-configurable test boards. Each test board includes at least one re-configurable test processor. The re-configurable test processors can communicate with one another using an inter-processor communication controller associated with each re-configurable test processor. The communication includes configuration information, control information, communication protocol information, stimulus data and responses. Configuration information and stimulus data can also be read from a memory. Configuration information is used to configure one or more re-configurable test processors. Once configured, the re-configurable test processor or processors process the data in order to generate one or more test signals. The one or more test signals are then used to test a device-under-test (DUT).
US 2006/0170435 A1 describes a programmable device to route signals on probe cards. A probe card of a waver test system includes one or more programmable integrated circuits (ICs) such as field-programmable-gate-arrays (FPGAs), to provide routing from individual test signal channels to one of multiple probes. The programmable integrated circuits can be placed on a base printed circuit board (PCB) of the probe card, or on a daughter card attached to the probe card. With programmability, the printed circuit board can be used to switch limited test system channels away from unused probes. Programmability further enables a single probe card to more effectively test devices having the same pad array, but having different pin-outs for different device options. Re-programmability also allows test engineers to re-program when debugging a test program.
US 2005/0024041 A1 describes a pin electronics interface circuit for use in an automated test equipment. The in electronics circuit includes a reconfigurable logic device in which different logic configurations may be installed to make measurements according to multiple tests to be applied to device-under-test. The pin electronics circuit comprises a level generating circuit coupled to the re-configurable logic device and configured to generate a number of test levels and a number of reference levels. The pin electronics circuit also comprises a switching circuit coupled to the re-configurable logic device and the level generating circuit, configured to receive the test levels and the reference levels, and controlled by the configurable logic device to selectively apply the test levels to the device-under-test according to a selected test, and to sense levels inputted to or outputted from the device-under-test by comparing the reference levels generated by the level generating circuit to the levels inputted to or outputted from the device-under-test.
The publication “The new ATE: protocol aware” of Andrew C. Evans (published: IEEE. International Test Conference, 2007. ITC 2007) describes an approach of a protocol-aware automated test equipment.
In view of the above discussion, there is a need for a cost efficient concept for providing a test circuit having a programmable protocol behavior and a good timing accuracy.